NAND Flash devices store information as charge in a NAND Flash cell. Multi-Level (MLC) NAND flash devices store k bits per cell using 2^k levels of charge. The amount of charge depends on the sequence of k bits being stored. For a certain sequence of k bits, the charge being stored may be distributed within a small range. FIG. 1 shows an example of a program level distribution 10 of a three bits per cell (bpc) MLC device—that includes 8 possible charge distributions (eight lobes denoted 11-18). As long as the charge distribution lobes are sufficiently distinct, the cell may be reliably read by read thresholds T1-T7 21-27.
The charge injection process is called programming. The programming process is simultaneously performed on a group of cells referred to here as a row. Furthermore, not all k bits within a cell are programmed simultaneously. In fact, each bit is of the k-bit sequence is stored in the row of cells during a separate programming operation.
FIG. 1 illustrates the bit by bit programming process of a 3 bpc MLC device. Initially, the LSB bit associated with each cell in the row is programmed. This is done by injecting charge if the bit is 0 and doing nothing if the LSB bit is 1. By the end of this programming step, each cell in the row contains charge distributed within the range given by one of the two lobes shown in program level distribution 30.
Subsequently, during a separate programming operation, the second (CSB) bit is programmed. This is done by injecting additional charge into the cell, depending on the CSB bit value and the previously programmed LSB bit. If the corresponding LSB bit was 1 and the CSB bit was 1, no additional charge is injected. If, the corresponding LSB bit was 1 and the CSB bit was 0, some additional charge may be injected such that the total charge in the cell is distributed within the range defined by the second lobe of program level distribution 40.
If, the corresponding LSB bit was 0 and the CSB bit was 0, a small amount of additional charge may be injected such that the total charge in the cell is distributed within the range defined by the third lobe of program level distribution 40.
If the corresponding LSB bit was 0 and the CSB bit was 1, a larger amount of additional charge may be injected such that the total charge in the cell is distributed within the range defined by the fourth lobe in the program level distribution 40.
By the end of this CSB programming stage, each cell in the row contains charge distributed within the range given by one of the four lobes program level distribution 40.
In a similar process, the third, most significant bit (MSB), is programmed during a third programming step. Following this last programming step, each cell in the row contains charge distributed within the range given by one of the eight lobes shown in program level distribution 50.
Each such programming step is associated with a page number. That is, a programming step may be a page programming step and the Flash memory device may be divided into erase blocks, each erase block contains a multiple of pages.
In addition, to reduce cell to cell coupling, the steps defined above will typically be separated by programming steps of other rows. For example, programming may begin with the LSB bits associated with row 0, then the LSB bits associated with row 1 and only then will the CSB bits of row 0 will be programmed.
Table 300 of FIG. 3 contains an example of a page programming ordering table for any given block according to an embodiment of the invention.
Each page is associated with a row, and an MSB, CSB or LSB bit.
In practice, each of the three programming steps described above is broken down into smaller steps. For example, the CSB page programming step will typically be broken down into three sub-steps where in the first sub-step (resulting in intermediate program level distribution 32), all cells associated with an LSB value of 1 and a CSB value of 0 are injected with charge corresponding to the second lobe of the middle graph of program level distribution 40.
In the second sub-step (resulting in intermediate program level distribution 34), all cells associated with an LSB value of 0 and a CSB value of 0 are injected with charge corresponding to the third lobe of program level distribution 40.
And in the third sub-step (resulting in program level distribution 40), all cells associated with an LSB value of 0 and a CSB value of 1 are injected with charge corresponding to the fourth lobe of program level distribution 34. This process is depicted in FIG. 4 which is more detailed than FIG. 2. FIG. 4 includes program level distribution 30, intermediate program level distributions 32 and 34 and program level distribution 40.
Similarly, FIG. 5 depicts an example of 7 MSB programming sub-steps A-G and includes corresponding program level distributions 40 and 110-170.
In practical embedded systems the programming may be interrupted due to a sudden power loss. From of FIGS. 4 and 5 it is apparent that if the programming operation is interrupted before it completes, the device may be left in such a state that previously stored data may not be reliably read out. For example, if the programming operation is interrupted during the MSB bit programming, just following programming sub-step C in FIG. 5 (program level distribution 130) the cells will be left in such a state such that two charge distribution lobes overlap. The first associated with LSB=1, CSB=0 and MSB=1 and the second lobe associated with LSB=0 and CSB=0.
Such a failure poses two problems associated with the interrupted row programming:                a. The thresholds needed to read the page are not the ones used to read the page after programming the LSB, CSB or MSB page but rather a mixture of them.        b. There is no threshold which distinctly distinguishes between LSB bits. Therefore, even with optimal thresholds, data stored in the LSB bits may not be reliably read out (i.e. it will contain errors far beyond the error correction capability of the ECC).        
The LSB bits in the above example may have been programmed a long time before the MSB bits but nevertheless, may be unreadable after interrupting the MSB bit programming. This type of failure is not acceptable in many applications and therefore, some measures are taken to handle loss of past information.